1. Field of the Invention
The present invention relates to programmable logic devices, and more specifically to a method for programming complex programmable logic devices having multiple function block types.
2. Background Art
Programmable logic devices (PLDs) are a class of integrated circuits (ICs) which can be programmed by a user to emulate various logic functions. Logic designers typically use PLDs to implement control logic in electronic systems because they are relatively easy to program, and often can be reprogrammed to change the emulated logic function. This makes their use in an electronic system's design phase less costly than custom hardwired or "application specific" integrated circuits (ASICs).
One major class of PLDs includes a set of input pins, a programmable AND plane connected to the input pins, an OR plane connected to output lines of the AND plane and a set of output pins connected to output lines of the OR plane. The AND plane provides a matrix of programmable connections where each column connects to an input pin and each row forms an output line of the AND plane, called a product term line, which connects to the OR plane. The OR plane may be programmable, such that each product term line is connectable to columns leading to different output pins, in which case the PLD is called a programmable logic array (PLA). Alternatively, the OR plane may be fixed, such that each product term line is assigned to a particular output pin, in which case the PLD is called a programmable array logic (PAL) device.
Because PLAs and PALs contain two levels of logic (AND and OR), these arrays are capable of implementing logic functions that are representable in a "sum of products" form. A sum of products form of a logic function is essentially a set of product terms (p-terms) for each output of the function. Such a logic function is represented in a PLD by programmed connections in the AND plane and OR plane. Each p-term line has a programmable input connection in the AND plane to each input pin and produces a single output value representing the logical AND or "product" of the connected inputs. Usually, both the original input pin value and its complement are available for connection to a p-term line. Each output has a programmable p-term connection in the OR plane and produces an output value representing the logical OR or "sum" of the connected p-terms.
These early PLDs were well-received by logic designers. However, as logic functions grew increasingly larger and more complex, logic designers were required to wire together two or more small PLDs to provide sufficient logic capacity. Although this process was tolerated during development and testing, it increased the cost and size of production units. This generated a demand for PLDs with increasingly larger logic capacity.
To meet the ever-increasing demand for greater capacity, PLDs with increasingly complex architectures have been developed. One popular complex PLD type, known as erasable programmable logic devices (EPLDs), includes a plurality of "function blocks," input/output (I/O) resources, and an interconnect matrix such that each of the function blocks is interconnectable to any other function block or I/O resource of an EPLD through the interconnect matrix. Each function block of an EPLD is structured like the two-level PLDs, described above. In effect, EPLDs incorporate several early PLDs and associated connection circuitry onto a single integrated circuit. This provides a circuit designer the convenience of implementing into a single device a complex logic function intended to program a wired collection of smaller PLDs using a single IC.
The function blocks of early EPLDs were essentially identical in size (capacity) and signal delay. Therefore, programming methods developed for these early EPLDs were primarily focused on implementing the desired logic functions into as few function blocks as possible, thereby leaving available as many resources of the EPLD as possible. One such prior art programming method is described in "A Fast Partitioning Method for PLA-Based FPGAs", IEEE Design & Test Of Computers, 1992, by Z. Hasan, D. Harrison, and M. Ciesielski.
More recently, a "Dual Block" EPLD was developed which includes two types of function blocks--a "fast" function block (FFB) whose architecture, in effect, sacrifices programmability for speed, and a "high density" function block (HDFB) whose architecture is designed for maximum programmability. This type of EPLD allows portions of a logic function requiring fast input-pin-to-output-pin times to be implemented by the FFBs, and the remaining portions of the logic function to be implemented by the HDFBs.
The above-mentioned prior art programming methods are inadequate for programming "Dual Block" EPLDs because these methods fail to consider the benefits of maximizing the use of one type of function block over the other.